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30614nk/82411sy/32311sy 20110303-s00009,20110316-s00001 no.a1936-1/24 semiconductor components industries, llc, 2014 march, 2014 http://onsemi.com ordering information see detailed ordering and shipping informa tion on page 24 of this data sheet. lv5234v overview the lv5234v is a 9-channel led driver ic that is capable of switching between constant-current output and open drain output. it enables 3-wire serial bus control (address designation)/i 2 c serial bus control to be set arbitrarily using an external pin. also possible are 9-channel led on/off c ontrol and the setting of the pwm luminance in 256 steps. the device also has a built-in fade-in/fade-out function. up to 32 driver ics can be connected using the slave address setting pins. function ? 9-channel output constant-current led driver/open drain output led driver (selected by using an external pin) supports separate on/off setting for each led output, high withstand voltage (vout<42v) ? in the constant-current mode (outsct: l), the reference current is set by the value of resistor connected to the external pin (rt1). built-in d/a (5 bits) for switching current level ? 0.96ma to 30.7ma (rgb drive) constant current (i o max=50ma) for full-color leds 9 channels ? in the open drain mode (outsct: h), high current drive (i o max=100ma) 9 channels ? luminance adjustment using internal pwm control (256 steps) ? 8-bit pwm luminance dimming (0% to 99.6%) ? 3-phase pwm ? fade-in/fade-out function (pwm control priority), supporting synchronous connection ? supports separate fade on/off for each led output (fade time commo n for all channels) ? interrupt control possible for fade function ? selection of 3-wire/i 2 c serial bus control signals enabled (switching using an external pin) slave addressing (5 bits, connection of up to 32 driver ics possible) ? low current consumption ? output malfunction protection circuits (thermal protection function, uvlo detection protection function) orderin g numbe r : ena1936b bi-cmos ic 9-channel led driver ssop30(275mil) * i 2 c bus is a trademark of philips corporation.
lv5234v no.a1936-2/24 specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage vcc max 6 v output voltage vo max led off 42 v output current io max 100 ma allowable power dissipation pd max ta 25 c * 0.84 w operating temperature topr -25 to +75 c storage temperature tstg -40 to +125 c * specified board : 114.3mm 76.1mm 1.6mm, glass epoxy board. [warning]: if you should intend to use this ic continuously under high temperature, high current, high voltage, or drastic temp erature change, even if it is used within the range of absolute maximum ratings or operating condit ions, there is a possibility of decrease reliability. please co ntact us for a confirmation. recommended operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage v cc sv cc 5.0 v operating supply voltage range v cc op sv cc 4.5 to 5.5 v electrical characteristics at ta = 25 c, v cc = 5v parameter symbol conditions ratings unit min typ max consumption current i cc 2 led off 3.5 5.5 ma oscillator frequency fosc 900 1000 1100 khz reference current pin voltage vrt rt1=22k 0.92 0.98 1.04 v max output current il v o =0.7 to 4.0v(same channel line regulation) -10 % between bits output current i o l i o =30.7ma (between bits pairing characteristics) 5% maximum led driver output current 1 imax1 led outsct= l 28.8 30.7 32.6 ma ledo output on resistance ron1 led1, led2, led3 (i o = 100ma) 4 10 off leak current ileak led off 10 a driver output malfunction protection voltage vt sv cc 2.58 2.70 2.82 v control circuit at ta = 25 c, v cc = 5.0v parameter symbol conditions ratings unit min typ max h level 1 vh1 input h level outsct 4.7 5 v l level 1 vl1 input l level outsct -0.2 0.3 v h level 2 vh2 input h level ctlsct 0.7 v cc v cc v l level 2 vl2 input l level ctlsct -0.2 0.3 v h level 3 vh3 input h level reset 0.8 v cc v cc v l level 3 vl3 input l level reset -0.2 0.2 v cc v h level 4 vh4 input h level sclk, sdata, sden 0.8 v cc v cc v l level 4 vl4 input l level sc lk, sdata, sden -0.2 0.2 v cc v h level 5 vh7 input h level a0 to a4 0.7 v cc v cc v l level 5 vl7 input l level a0 to a4 -0.2 0.3 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lv5234v no.a1936-3/24 package dimensions unit : mm ssop30 (275mil) case 565at issue a soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. (unit: mm) 7.00 0.32 1.00 0.65 xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxxxx ymddd
lv5234v no.a1936-4/24 block diagram pin assignment 30 1 sv cc osc_out 29 2 sclk outsct 28 3 sdata ct 27 4 sden rt1 22 7 pgnd1 ledb3 21 8 ledr3 pgnd3 20 9 ledg3 ledb2 19 10 a0 ledb1 top view 5 6 11 12 13 14 15 26 25 24 23 18 17 16 nc ledr1 ledr2 ledg1 pgnd2 ledg2 a1 a2 a3 a4 sgnd ctlsct reset test pd max -- ta 0 0.42 1.0 0.2 1.2 --25 75 25 50 0 100 0.4 0.6 0.8 0.84 ambient temperature , ta -- c allowable power dissipation, pd max -- w specified board : 114.3 76.1 1.6mm 3 glass epoxy bgr a4 a3 a2 a1 a0 sclk sdata ctlsct reset test outsct sv cc sgnd osc_out ct rt1 osc i-reg d/a serial bus i/f protection tsd uvlo pwm brightness fade-in/out control sden nc rled-d/a gled-d/a bled-d/a ledr1 ledr2 ledr3 pgnd1 ledg1 ledg2 ledg3 pgnd2 ledb1 ledb2 ledb3 pgnd3
lv5234v no.a1936-5/24 pin descriptions pin no. pin name i/o description 1 sv cc - power supply pin 2 sclk i serial clock signal input pin 3 sdata i serial data signal input pin 4 sden i serial enable signal input pin 5 nc - no connection 6 ledr1 o ledr1 output pin 7 ledr2 o ledr2 output pin 8 pgnd1 - gnd pin dedicated for led driver 9 ledr3 o ledr3 output pin 10 ledg1 o ledg1 output pin 11 ledg2 o ledg2 output pin 12 pgnd2 - gnd pin dedicated for led driver 13 ledg3 o ledg3 output pin 14 a0 i slave address input pin a0 15 a1 i slave address input pin a1 16 a2 i slave address input pin a2 17 a3 i slave address input pin a3 18 a4 i slave address input pin a4 19 ledb1 o ledb1 output pin 20 ledb2 o ledb2 output pin 21 pgnd3 - gnd pin dedicated for led driver 22 ledb3 o ledb3 output pin 23 ctlsct i 3-wire serial bus/i 2 c serial bus selecting control pin (l: 3-wire serial, h: i 2 c) 24 sgnd - analog circuit gnd pin 25 test i test pin (connected to gnd) 26 reset i reset signal input pin 27 rt1 o led current setting resistor connection pin 1 28 ct o oscillation frequency setting capacitor connection pin 29 outsct i output type switching control pin l: constant-current output h: open drain output 30 osc_out o oscillator output pin (synchronous connection) outsct settings at sv cc =5.0v led driver out p ut pin outsct p in led1 , led2 , led3 l=-0.2 to 0.3v constant current output built-in current value switching d/a (5 bits) 0.96ma to 30.7ma , rt1=22k ? ( f=1mhz ) h=4.7 to 5.0v open drain output current value is determined by external limiting resistor. ron=4 ?
lv5234v no.a1936-6/24 pin functions pin no. pin name pin function equivalent circuit 1 sv cc power supply pin 2 3 4 sclk sdata sden serial clock signal input pin serial data signal input pin serial enable signal input pin sv cc 14 15 16 17 18 23 29 a0 a1 a2 a3 a4 ctlsct outsct slave address setting pin a0 slave address setting pin a1 slave address setting pin a2 slave address setting pin a3 slave address setting pin a4 serial bus communication setting pin when set to low: the 3-wire serial bus signals are set as the input signals. when set to high: the i 2 c serial bus signals are set as the input signals. led driver output type setting pin when set to low: constant-current output is set for the led driver. when set to high: open drain output is set for the led driver. sv cc 24 sgnd gnd pin 25 test test pin this pin must always be connected to gnd. sv cc 26 reset reset signal input pin reset status when set to low. sv cc 27 rt1 reference current setting resistor connection pin. by connecting the external register between this pin and gnd, the reference current is generated. the pin voltage is approximately 0.98v. by changing the current level, it is possible to change the oscillator frequency and led driver current value (in the constant-current mode). sv cc continued on next page.
lv5234v no.a1936-7/24 continued from preceding page. pin no. pin name pin function equivalent circuit 28 ct oscillator frequency setting capacitor connection pin/oscillator input pin. by changing the value of capacitance, it is possible to change the oscillator frequency. the capacitor must be connected to this pin of the master-side ic. the ct pin of the slave-side ic must be connected as the oscillator input pin. sv cc + - + - internal reference 30 osc_out oscillator output pin when a multiple number of driver ics are connected for use, the oscillators can be connected in synchronization by connecting the osc_out output to the ct pin of the ics to be connected. sv cc 6 7 9 10 11 13 19 20 22 ledr1 ledr2 ledr3 ledg1 ledg2 ledg3 ledb1 ledb2 ledb3 ledr1 output pin ledr2 output pin ledr3 output pin ledg1 output pin ledg2 output pin ledg3 output pin ledb1 output pin ledb2 output pin ledb3 output pin if these pins are not going to be used, they must always be connected to gnd. 8 12 21 pgnd1 pgnd2 pgnd3 gnd pin dedicate for ledr gnd pin dedicate for ledg gnd pin dedicate for ledb 5 nc no connection
lv5234v no.a1936-8/24 application circuit diagrams specifications when one driver ic is used use as a master-side ic slave selection: a0-a4: low address setting: master (010-0000) nothing must be connected to the nc pins specifications when more than one driver ic is used use as a master-side ic slave selection: a0 : high a1-a4: low address setting: master (010-0000) use as a slave-side ic slave selection: a0 high: a1-a4 low address setting: slave (010-0001) the oscillator frequency is determined by the master ic. the synchronous connection of the oscillator can be established by connecting the oscillator output (osc_out) to the ct pins of the slave-side ics. nothing must be connected to the nc pins. 30 1 sv cc osc_out 29 2 sclk outsct 28 3 sdata ct 27 4 sden rt1 22 7 pgnd1 ledb3 21 8 ledr3 pgnd3 20 9 ledg3 ledb2 19 10 a0 ledb1 5 6 11 12 13 14 15 26 25 24 23 18 17 16 nc ledr1 ledr2 ledg1 pgnd2 ledg2 a1 a2 a3 a4 sgnd ctlsct reset test 5v 5v 100pf 5v i 2 c serial bus micon vled 30 1 sv cc osc_out 29 2 sclk outsct 28 3 sdata ct 27 4 sden rt1 22 7 pgnd1 ledb3 21 8 ledr3 pgnd3 20 9 ledg3 ledb2 19 10 a0 ledb1 5 6 11 12 13 14 15 26 25 24 23 18 17 16 nc ledr1 ledr2 ledg1 pgnd2 ledg2 a1 a2 a3 a4 sgnd ctlsct reset test 5v 5v 100pf 5v i 2 c serial bus micon 30 1 sv cc osc_out 29 2 sclk outsct 28 3 sdata ct 27 4 sden rt1 22 7 pgnd1 ledb3 21 8 ledr3 pgnd3 20 9 ledg3 ledb2 19 10 a0 ledb1 5 6 11 12 13 14 15 26 25 24 23 18 17 16 nc ledr1 ledr2 ledg1 pgnd2 ledg2 a1 a2 a3 a4 sgnd ctlsct reset test 5v 5v 5v vled
lv5234v no.a1936-9/24 serial bus communication specifications 1) 3-wire serial bus transfer timing conditions parameter symbol conditions min. typ. max. unit cycle time tcy1 sclk clock period 200 - - ns data setup time ts0 sden setup time relative to the rise of sclk 90 - - ns ts1 sdata setup time relative to the rise of sclk 60 - - ns data hold time th0 sden hold time relative to the fall of sclk 200 - - ns th1 sdata hold time relative to the fall of sclk 60 - - ns pulse width tw1l low period pulse width of sclk 90 - - ns tw1h high period pulse width of sclk 90 - - ns tw2l low period pulse width of sden 1 - - s data length: 24 bits clock frequency: 5 mhz or less when 24 sclk clock signals have been input during the high period of sden, the sdata is taken in at the rising edge of sclk. note: if the number of sclk clock signals during the high period of sden is 23 or less, sdata is not taken in. if it is 25 or more, the register address is automatically incremented every time 1 byte is taken in. the slave address is assigned by the first byte, and the register address on the serial map is specified by the next byte. the third byte transfers the data to the address specified by th e register address that was written by the second byte and if t he data subsequently continues even after this, the register addr ess is automatically incremented for the fourth and subsequent bytes. as a result, it is possible to send the data continuously from the specified addresses. data of less than one byte is ig nored. however, when the address reach es 15h, in the next byte to be transferred becomes 00h. tw2h sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sa7 ts0 ts1 th1 tcy1 tw1l tw1h th0 50% sden sclk sdata 0 1 0 0 0 0 1 - 0 0 0 0 0 1 1 1 sdata sden sdata sden example of a write operation: data1 slave address register address 07h is set data is written into address 07h. data2 data3 data data is written into address 08h. data is written into address 09h. ignore if data is less than 1 byte.
lv5234v no.a1936-10/24 2) i 2 c serial transfer timing conditions standard mode parameter symbol conditions min. typ. max. unit scl clock frequency fsc1 sc l clock frequency 0 - 100 khz data setup time ts1 scl setup time relative to the fall of sda 4.7 - - s ts2 sda setup time relative to the rise of scl 250 - - ns ts3 scl setup time relative to the rise of sda 4.0 - - s data hold time th1 scl hold time relative to the fall of sda 4.0 - - s th2 sda hold time relative to the fall of scl 0 - - s pulse width twl scl pulse width for the l period 4.7 - - s twh scl pulse width for the h period 4.0 - - s input waveform conditions ton scl and sda (input) rise time - - 1000 ns tof scl and sda (input) fall time - - 300 ns bus free time tbuf time between stop condition and start condition 4.7 - - s high-speed mode parameter symbol conditions min. typ. max. unit scl clock frequency fsc1 sc l clock frequency 0 - 400 khz data setup time ts1 scl setup time relative to the fall of sda 0.6 - - s ts2 sda setup time relative to the rise of scl 100 - - ns ts3 scl setup time relative to the rise of sda 0.6 - - s data hold time th1 scl hold time relative to the fall of sda 0.6 - - s th2 sda hold time relative to the fall of scl 0 - - s pulse width twl scl pulse width for the l period 1.3 - - s twh scl pulse width for the h period 0.6 - - s input waveform conditions ton scl and sda (input) rise time - - 300 ns tof scl and sda (input) fall time - - 300 ns bus free time tbuf time between st op and start conditions 1.3 - - s th1 ts2 twl th2 twh th1 ts1 ts3 tbuf scl sda ton tof start condition stop condition input waveform condition resend start condition
lv5234v no.a1936-11/24 i 2 c bus transfer method start and stop conditions during data transfer operation using the i 2 c bus, sda must basically be kept in constant state while scl is ?h? as shown below. when data is not being transferred, both scl and sda are set in the ?h? state. when scl=sda is ?h,? the start condition is established wh en sda is changed from ?h? to ?l,? and access is started. when scl is ?h,? the stop condition is established when sda is changed from ?l? to ?h,? and access is ended. data transfer and acknowledgement response after the start condition has been established, the data is transferred one byte (8 bits) at a time. any number of bytes of data can be transferred continuously. each time the 8-bit data is transferred, the ack signal is sent from the receive side to the send side. the ack signal is issued when sda on the send side is released and sda on the receive side is set to ?l? immediately after fall of the clock pulse at the scl eighth b it of data transfer to ?l.? when the next 1-byte transfer is left in the receive state after sending the ack signal from the receive side, the receive side releases sda at the fall of the scl ninth clock. in the i 2 c bus, there is no ce signal. in its place, a 7-bit slave address is assigned to each device, and the first byte of transfer is assigned to the command (r/w) representing the 7-bit address and subseq uent transfer direction. note that only write is valid in this ic. the 7-bit address is transferre d sequentially starting with msb, and the eighth bit is set to ?l? which indicates a write. ts2 th2 scl sda th1 scl sda ts3 start condition stop condition scl sda start m s b l s b w a c k m s b l s b a c k m s b l s b a c k stop slave address register address data
lv5234v no.a1936-12/24 slave address condition slave address sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 resister name - - a4 a3 a2 a1 a0 - default 0 1 0 0 0 0 0 - terminal pin :lv5234 a4 a3 a2 a1 a0 sa7 sa6 sa5 sa4 sa3 sa2 sa1 sa0 l l l l l 0 1 0 0 0 0 0 - l l l l h 0 1 0 0 0 0 1 - l l l h l 0 1 0 0 0 1 0 - l l l h h 0 1 0 0 0 1 1 - l l h l l 0 1 0 0 1 0 0 - l l h l h 0 1 0 0 1 0 1 - l l h h l 0 1 0 0 1 1 0 - l l h h h 0 1 0 0 1 1 1 - l h l l l 0 1 0 1 0 0 0 - l h l l h 0 1 0 1 0 0 1 - l h l h l 0 1 0 1 0 1 0 - l h l h h 0 1 0 1 0 1 1 - l h h l l 0 1 0 1 1 0 0 - l h h l h 0 1 0 1 1 0 1 - l h h h l 0 1 0 1 1 1 0 - l h h h h 0 1 0 1 1 1 1 - h l l l l 0 1 1 0 0 0 0 - h l l l h 0 1 1 0 0 0 1 - h l l h l 0 1 1 0 0 1 0 - h l l h h 0 1 1 0 0 1 1 - h l h l l 0 1 1 0 1 0 0 - h l h l h 0 1 1 0 1 0 1 - h l h h l 0 1 1 0 1 1 0 - h l h h h 0 1 1 0 1 1 1 - h h l l l 0 1 1 1 0 0 0 - h h l l h 0 1 1 1 0 0 1 - h h l h l 0 1 1 1 0 1 0 - h h l h h 0 1 1 1 0 1 1 - h h h l l 0 1 1 1 1 0 0 - h h h l h 0 1 1 1 1 0 1 - h h h h l 0 1 1 1 1 1 0 - h h h h h 0 1 1 1 1 1 1 -
lv5234v no.a1936-13/24 serial each mode setting address : 00h d7 d6 d5 d4 d3 d2 d1 d0 re g ister name - pwm [ 2 ] pwm [ 1 ] pwm [ 0 ] - - mas - default 0 0 0 0 0 0 0 0 d6 d5 d4 time(ms) pwm cycle setting 0 0 0 0.5 *default 0 0 1 1.0 0 1 0 2.0 0 1 1 4.0 1 0 0 8.0 - - - - - - - - - - - - - - - - d1 mas master/slave setting 0 master *default 1 slave address : 01h d7 d6 d5 d4 d3 d2 d1 d0 register name - fout[2] fout[1] fo ut[0] - fin[2] fin[1] fin[0] default 0 0 0 0 0 0 0 0 d6 d5 d4 time(ms) fout slope setting 0 0 0 no slope *default 0 0 1 0.5 0 1 0 1.0 0 1 1 2.0 1 0 0 4.0 1 0 1 8.0 1 1 0 16.0 1 1 1 32.0 speed of fade a step (it takes 256 above-mentioned, set value seconds until the fade is completed.) d2 d1 d0 time(ms) fin slope setting 0 0 0 no slope *default 0 0 1 0.5 0 1 0 1.0 0 1 1 2.0 1 0 0 4.0 1 0 1 8.0 1 1 0 16.0 1 1 1 32.0 speed of fade a step (it takes 256 above-mentioned, set value seconds until the fade is completed.)
lv5234v no.a1936-14/24 address : 02h d7 d6 d5 d4 d3 d2 d1 d0 register name - - - rled[4] rled[3] rled[2] rled[1] rled[0] default 0 0 0 0 0 0 0 0 d4 d3 d2 d1 d0 current value (m a) rled current value setting 0 0 0 0 0 0.96 * default 0 0 0 0 1 1.92 0 0 0 1 0 2.88 0 0 0 1 1 3.84 0 0 1 0 0 4.80 0 0 1 0 1 5.76 0 0 1 1 0 6.72 0 0 1 1 1 7.68 0 1 0 0 0 8.64 0 1 0 0 1 9.60 0 1 0 1 0 10.56 0 1 0 1 1 11.52 0 1 1 0 0 12.48 0 1 1 0 1 13.44 0 1 1 1 0 14.40 0 1 1 1 1 15.36 1 0 0 0 0 16.32 1 0 0 0 1 17.28 1 0 0 1 0 18.24 1 0 0 1 1 19.20 1 0 1 0 0 20.16 1 0 1 0 1 21.12 1 0 1 1 0 22.08 1 0 1 1 1 23.04 1 1 0 0 0 24.00 1 1 0 0 1 24.96 1 1 0 1 0 25.92 1 1 0 1 1 26.88 1 1 1 0 0 27.84 1 1 1 0 1 28.80 1 1 1 1 0 29.76 1 1 1 1 1 30.72
lv5234v no.a1936-15/24 address : 03h d7 d6 d5 d4 d3 d2 d1 d0 register name - - - gled[4] gled[3] gled[2] gled[1] gled[0] default 0 0 0 0 0 0 0 0 d4 d3 d2 d1 d0 current value (m a) gled current value setting 0 0 0 0 0 0.96 * default 0 0 0 0 1 1.92 0 0 0 1 0 2.88 0 0 0 1 1 3.84 0 0 1 0 0 4.80 0 0 1 0 1 5.76 0 0 1 1 0 6.72 0 0 1 1 1 7.68 0 1 0 0 0 8.64 0 1 0 0 1 9.60 0 1 0 1 0 10.56 0 1 0 1 1 11.52 0 1 1 0 0 12.48 0 1 1 0 1 13.44 0 1 1 1 0 14.40 0 1 1 1 1 15.36 1 0 0 0 0 16.32 1 0 0 0 1 17.28 1 0 0 1 0 18.24 1 0 0 1 1 19.20 1 0 1 0 0 20.16 1 0 1 0 1 21.12 1 0 1 1 0 22.08 1 0 1 1 1 23.04 1 1 0 0 0 24.00 1 1 0 0 1 24.96 1 1 0 1 0 25.92 1 1 0 1 1 26.88 1 1 1 0 0 27.84 1 1 1 0 1 28.80 1 1 1 1 0 29.76 1 1 1 1 1 30.72
lv5234v no.a1936-16/24 address : 04h d7 d6 d5 d4 d3 d2 d1 d0 register name - - - bled[4] bl ed[3] bled[2] bled[1] bled[0] default 0 0 0 0 0 0 0 0 d4 d3 d2 d1 d0 current value (m a) bled current value setting 0 0 0 0 0 0.96 * default 0 0 0 0 1 1.92 0 0 0 1 0 2.88 0 0 0 1 1 3.84 0 0 1 0 0 4.80 0 0 1 0 1 5.76 0 0 1 1 0 6.72 0 0 1 1 1 7.68 0 1 0 0 0 8.64 0 1 0 0 1 9.60 0 1 0 1 0 10.56 0 1 0 1 1 11.52 0 1 1 0 0 12.48 0 1 1 0 1 13.44 0 1 1 1 0 14.40 0 1 1 1 1 15.36 1 0 0 0 0 16.32 1 0 0 0 1 17.28 1 0 0 1 0 18.24 1 0 0 1 1 19.20 1 0 1 0 0 20.16 1 0 1 0 1 21.12 1 0 1 1 0 22.08 1 0 1 1 1 23.04 1 1 0 0 0 24.00 1 1 0 0 1 24.96 1 1 0 1 0 25.92 1 1 0 1 1 26.88 1 1 1 0 0 27.84 1 1 1 0 1 28.80 1 1 1 1 0 29.76 1 1 1 1 1 30.72
lv5234v no.a1936-17/24 address : 05h d7 d6 d5 d4 d3 d2 d1 d0 register name - b2on g2on r2on - b1on g1on r1on default 0 0 0 0 0 0 0 0 d6 b2on ledb2 on/off setting 0 off * default 1 on d5 g2on ledg2 on/off setting 0 off * default 1 on d4 r2on ledr2 on/off setting 0 off * default 1 on d2 b1on ledb1 on/off setting 0 off * default 1 on d1 g1on ledg1on/off setting 0 off * default 1 on d0 r1on ledr1 on/off setting 0 off * default 1 on address : 06h d7 d6 d5 d4 d3 d2 d1 d0 register name - - - - - b3on g3on r3on default 0 0 0 0 0 0 0 0 d2 b3on ledb3 on/off setting 0 off * default 1 on d1 g3on ledg3 on/off setting 0 off * default 1 on d0 r3on ledr3 on/off setting 0 off * default 1 on
lv5234v no.a1936-18/24 address : 07h d7 d6 d5 d4 d3 d2 d1 d0 register name - - r3pon[1] r3pon[0] r2 pon[1] r2pon[0] r1 pon[1] r1pon[0] default 0 0 0 0 0 0 0 0 d5 d4 r3pon ledr3 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - d3 d2 r2pon ledr2 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - d1 d0 r1pon ledr1 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - address : 08h d7 d6 d5 d4 d3 d2 d1 d0 register name - - g3pon[1] g3pon[0] g2pon[1] g2pon[0] g1pon[1] g1pon[0] default 0 0 0 0 0 0 0 0 d5 d4 g3pon ledg3 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - d3 d2 g2pon ledg2 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - d1 d0 g1pon ledg1 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - -
lv5234v no.a1936-19/24 address : 09h d7 d6 d5 d4 d3 d2 d1 d0 register name - - b3pon[1] b3pon[0] b2pon[1] b2pon[0] b1pon[1] b1pon[0] default 0 0 0 0 0 0 0 0 d5 d4 b3pon ledb3 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - d3 d2 b2pon ledb2 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - - d1 d0 b1pon ledb1 output setting 0 0 pmw output priority * default 0 1 fade output priority 1 0 compulsion on/off output priority - - -
lv5234v no.a1936-20/24 address : 0ah d7 d6 d5 d4 d3 d2 d1 d0 register name - r3cm r2cm r1cm - r3fd r2fd r1fd default 0 0 0 0 0 0 0 0 d6 r3cm ledr3 compulsion on/off setting 0 compulsion off * default 1 compulsion on d5 r2cm ledr2 compulsion on/off setting 0 compulsion off * default 1 compulsion on d4 r1cm ledr1 compulsion on/off setting 0 compulsion off * default 1 compulsion on d2 r3fd ledr3 fade function on/off setting 0 fade invalidity * default 1 fade effective d1 r2fd ledr2 fade function on/off setting 0 fade invalidity * default 1 fade effective d0 r1fd ledr1 fade function on/off setting 0 fade invalidity * default 1 fade effective address : 0bh d7 d6 d5 d4 d3 d2 d1 d0 register name - g3cm g2cm g1cm - g3fd g2fd g1fd default 0 0 0 0 0 0 0 0 d6 g3cm ledg3 compulsion on/off setting 0 compulsion off * default 1 compulsion on d5 g2cm ledg2 compulsion on/off setting 0 compulsion off * default 1 compulsion on d4 g1cm ledg1 compulsion on/off setting 0 compulsion off * default 1 compulsion on d2 g3fd ledg3 fade function on/off setting 0 fade invalidity * default 1 fade effective d1 g2fd ledg2 fade function on/off setting 0 fade invalidity * default 1 fade effective d0 g1fd ledg1 fade function on/off setting 0 fade invalidity * default 1 fade effective
lv5234v no.a1936-21/24 address : 0ch d7 d6 d5 d4 d3 d2 d1 d0 register name - b3cm b2cm b1cm - b3fd b2fd b1fd default 0 0 0 0 0 0 0 0 d6 b3cm ledb3 compulsion on/off setting 0 compulsion off * default 1 compulsion on d5 b2cm ledb2 compulsion on/off setting 0 compulsion off * default 1 compulsion on d4 b1cm ledb1 compulsion on/off setting 0 compulsion off * default 1 compulsion on d2 b3fd ledb3 fade function on/off setting 0 fade invalidity * default 1 fade effective d1 b2fd ledb2 fade function on/off setting 0 fade invalidity * default 1 fade effective d0 b1fd ledb1 fade function on/off setting 0 fade invalidity * default 1 fade effective address : 0dh d7 d6 d5 d4 d3 d2 d1 d0 register name r1pwm[7] r1pwm[6] r1pwm[5] r1pwm[4] r1pwm[3] r1pwm[2] r1pwm[1] r1pwm[0] default 0 0 0 0 0 0 0 0 ledr1 pwm duty setting (default all0) d duty (%) duty (%) = r1pwm[7:0] 256 00h 0.0 ffh 99.6 address : 0eh d7 d6 d5 d4 d3 d2 d1 d0 register name g1pwm[7] g1pwm[6] g1pwm[5] g1pwm[4] g1pwm[3] g1pwm[2] g1pwm[1] g1pwm[0] default 0 0 0 0 0 0 0 0 ledg1 pwm duty setting (default all0) d duty (%) duty (%) = g1pwm[7:0] 256 00h 0.0 ffh 99.6 address : 0fh d7 d6 d5 d4 d3 d2 d1 d0 register name b1pwm[7] b1pwm[6] b1pwm[5] b1pwm[4] b1pwm[3] b1pwm[2] b1pwm[1] b1pwm[0] default 0 0 0 0 0 0 0 0 ledb1 pwm duty setting (default all0) d duty (%) duty (%) = b1pwm[7:0] 256 00h 0.0 ffh 99.6
lv5234v no.a1936-22/24 address : 10h d7 d6 d5 d4 d3 d2 d1 d0 register name r2pwm[7] r2pwm[6] r2pwm[5] r2pwm[4] r2pwm[3] r2pw m[2] r2pwm[1] r2pwm[0] default 0 0 0 0 0 0 0 0 ledr2 pwm duty setting (default all0) d duty (%) duty (%) = r2pwm[7:0] 256 00h 0.0 ffh 99.6 address : 11h d7 d6 d5 d4 d3 d2 d1 d0 register name g2pwm[7] g2pwm[6] g2pwm[5] g2pwm[4] g2pwm[3] g2pwm[2] g2pwm[1] g2pwm[0] default 0 0 0 0 0 0 0 0 ledg2 pwm duty setting (default all0) d duty (%) duty (%) = g2pwm[7:0] 256 00h 0.0 ffh 99.6 address : 12h d7 d6 d5 d4 d3 d2 d1 d0 register name b2pwm[7] b2pwm[6] b2pwm[5] b2pwm[4] b2pwm[3] b2pwm[2] b2pwm[1] b2pwm[0] default 0 0 0 0 0 0 0 0 ledb2 pwm duty setting (default all0) d duty (%) duty (%) = b2pwm[7:0] 256 00h 0.0 ffh 99.6 address : 13h d7 d6 d5 d4 d3 d2 d1 d0 register name r3pwm[7] r3pwm[6] r3pwm[5] r3pwm[4] r3pwm[3] r3pw m[2] r3pwm[1] r3pwm[0] default 0 0 0 0 0 0 0 0 ledr3 pwm duty setting (defaultall0) d duty (%) duty (%) = r3pwm[7:0] 256 00h 0.0 ffh 99.6 address : 14h d7 d6 d5 d4 d3 d2 d1 d0 register name g3pwm[7] g3pwm[6] g3pwm[5] g3pwm[4] g3pwm[3] g3pwm[2] g3pwm[1] g3pwm[0] default 0 0 0 0 0 0 0 0 ledg3 pwm duty setting (default all0) d duty (%) duty (%) = g3pwm[7:0] 256 00h 0.0 ffh 99.6 address : 15h d7 d6 d5 d4 d3 d2 d1 d0 register name b3pwm[7] b3pwm[6] b3pwm[5] b3pwm[4] b3pwm[3] b3pwm[2] b3pwm[1] b3pwm[0] default 0 0 0 0 0 0 0 0 ledb3 pwm duty setting (default all0) d duty (%) duty (%) = b3pwm[7:0] 256 00h 0.0 ffh 99.6
lv5234v no.a1936-23/24 lv5234v serial map ? table upper row: register name table the lower: default value a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 00h 0 0 0 0 0 0 0 0 pwm[2:0] mas 0 0 0 0 0 0 0 0 01h 0 0 0 0 0 0 0 1 fout[2:0] fin[2:0] 0 0 0 0 0 0 0 0 02h 0 0 0 0 0 0 1 0 rled[4:0] 0 0 0 0 0 0 0 0 03h 0 0 0 0 0 0 1 1 gled[4:0] 0 0 0 0 0 0 0 0 04h 0 0 0 0 0 1 0 0 bled[4:0] 0 0 0 0 0 0 0 0 05h 0 0 0 0 0 1 0 1 b2on g2on r2on b1on g1on r1on 0 0 0 0 0 0 0 0 06h 0 0 0 0 0 1 1 0 b3on g3on r3on 0 0 0 0 0 0 0 0 07h 0 0 0 0 0 1 1 1 r3pon[1:0] r2pon[1:0] r1pon[1:0] 0 0 0 0 0 0 0 0 08h 0 0 0 0 1 0 0 0 g3pon[1:0] g2pon[1:0] g1pon[1:0] 0 0 0 0 0 0 0 0 09h 0 0 0 0 1 0 0 1 b3pon[1:0] b2pon[1:0] b1pon[2:0] 0 0 0 0 0 0 0 0 0ah 0 0 0 0 1 0 1 0 r3cm r2cm r1cm r3fd r2fd r1fd 0 0 0 0 0 0 0 0 0bh 0 0 0 0 1 0 1 1 g3cm g2cm g1cm g3fd g2fd g1fd 0 0 0 0 0 0 0 0 0ch 0 0 0 0 1 1 0 0 b3cm b2cm b1cm b3fd b2fd b1fd 0 0 0 0 0 0 0 0 0dh 0 0 0 0 1 1 0 1 r1pwm[7:0] 0 0 0 0 0 0 0 0 0eh 0 0 0 0 1 1 1 0 g1pwm[7:0] 0 0 0 0 0 0 0 0 0fh 0 0 0 0 1 1 1 1 b1pwm[7:0] 0 0 0 0 0 0 0 0 10h 0 0 0 1 0 0 0 0 r2pwm[7:0] 0 0 0 0 0 0 0 0 11h 0 0 0 1 0 0 0 1 g2pwm[7:0] 0 0 0 0 0 0 0 0 12h 0 0 0 1 0 0 1 0 b2pwm[7:0] 0 0 0 0 0 0 0 0 13h 0 0 0 1 0 0 1 1 r3pwm[7:0] 0 0 0 0 0 0 0 0 14h 0 0 0 1 0 1 0 0 g3pwm[7:0] 0 0 0 0 0 0 0 0 15h 0 0 0 1 0 1 0 1 b3pwm[7:0] 0 0 0 0 0 0 0 0 register address data
lv5234v ps no.a1936-24/24 ordering information device package shipping (qty / packing) lv5234v-mpb-h ssop30 (275mil) (pb-free / halogen free) 48 / fan-fold lv5234v-tlm-h ssop30 (275mil) (pb-free / halogen free) 1000 / tape & reel lv5234vz-mpb-h ssop30 (275mil) (pb-free / halogen free) 48 / fan-fold LV5234VZ-TLM-H ssop30 (275mil) (pb-free / halogen free) 1000 / tape & reel on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for an y such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona linjuryor death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale i n any manner.

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